Spatial Data Locality with Respect to Degree of Parallelism in Processor-and-Memory Hierarchies

A system organized as a Hierarchy of Processor-And-Memory (HPAM) extends the familiar notion of memory hierarchy by including processors with di erent performance in di erent levels of the hierarchy. Tasks are assigned to di erent hierarchy levels according to their degree of parallelism. This paper studies the spatial locality (with respect to degree of parallelism) behavior of simulated parallelized benchmarks in multi-level HPAM systems, and presents an inter-level cache coherence protocol that supports inclusion and multiple block sizes on an HPAM architecture. Inter-level miss rates and tra c simulation results show that the use of multiple data transfer sizes (as opposed to a unique size) across the HPAM hierarchy allows the reduction of data tra c between the uppermost levels in the hierarchy while not degrading the miss rate in the lowest level.